Differences

This shows you the differences between two versions of the page.

--- azonenberg:microchip:enc424j600 [2014/03/27 05:52] – azonenberg
+++ azonenberg:microchip:enc424j600 [2024/07/08 16:56] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
-{{tag>collection_az vendor_microchip type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_unknown tech_250nm}}
+{{tag>collection_az vendor_microchip type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_tsmc tech_180nm}}
 /100mbit SPI/parallel Ethernet controller.
-Same 250 nm process technology as the PIC32MX series.
 ====== Package ======
@@ Line 15: / Line 13: @@
 Rough stitch of old images with Am10x objective. Need to re-shoot at higher resolution.
-[[http://siliconpr0n.org/map/microchip/enc424j600/top_metal_am10x/|Map]]
+[[http://siliconpr0n.org/map/microchip/enc424j600/mz_am10x/|Map]]
 {{:azonenberg:microchip:enc424j600-m3-100x-cropped-4k.jpg?600|}}
@@ Line 27: / Line 25: @@
 Partial HF delayer of SRAM. Confirmed to be same process as PIC32 based on SRAM cell pitch.
-{{:azonenberg:microchip:enc424j600_sram_01_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:microchip:enc424j600_sram_01_bf_neo40x_annotated.jpg?600|}}{{https://siliconpr0n.org/map/microchip/enc424j600/single/microchip_enc424j600_azonenberg_mz_mit20x.thumb.jpg}}
+[[https://siliconpr0n.org/map/microchip/enc424j600/azonenberg_mz_mit20x/|mz_mit20x]]
+  * [[https://siliconpr0n.org/map/microchip/enc424j600/single/microchip_enc424j600_azonenberg_mz_mit20x.jpg|Single]] (14712x14989, 31.447MiB)