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azonenberg:nvidia:mcpx [2014/03/09 20:18] azonenbergazonenberg:nvidia:mcpx [2015/01/04 22:50] (current) – external edit 127.0.0.1
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   * M5 = medium-range vertical interconnect   * M5 = medium-range vertical interconnect
   * M4 = medium-range horizontal interconnect   * M4 = medium-range horizontal interconnect
-  * M3 = short-range horizontal interconnect +  * M3 = short-range vertical interconnect 
-  * M2 = short-range vertical interconnect+  * M2 = short-range horizontal interconnect
   * M1 = intra-cell routing   * M1 = intra-cell routing
  
azonenberg/nvidia/mcpx.1394396317.txt.gz · Last modified: 2014/03/09 20:18 by azonenberg