Silicon Pr0n

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{{tag>collection_az vendor_microchip type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_tsmc tech_180nm}}

10/100mbit SPI/parallel Ethernet controller.

====== Package ======

44-pin QFN, decapped live.

{{:azonenberg:microchip:s7300480_cropped.jpg?600|}}

====== Die ======

Rough stitch of old images with Am10x objective. Need to re-shoot at higher resolution.

[[http://siliconpr0n.org/map/microchip/enc424j600/mz_am10x/|Map]]

{{:azonenberg:microchip:enc424j600-m3-100x-cropped-4k.jpg?600|}}

Close-up of dense logic area at upper right:

{{:azonenberg:microchip:enc424j600_02_bf_neo40x_annotated.jpg?600|}}

{{:azonenberg:microchip:enc424j600_01_bf_neo40x_annotated.jpg?600|}}

Partial HF delayer of SRAM. Confirmed to be same process as PIC32 based on SRAM cell pitch.

{{:azonenberg:microchip:enc424j600_sram_01_bf_neo40x_annotated.jpg?600|}}{{https://siliconpr0n.org/map/microchip/enc424j600/single/microchip_enc424j600_azonenberg_mz_mit20x.thumb.jpg}}

[[https://siliconpr0n.org/map/microchip/enc424j600/azonenberg_mz_mit20x/|mz_mit20x]]

  * [[https://siliconpr0n.org/map/microchip/enc424j600/single/microchip_enc424j600_azonenberg_mz_mit20x.jpg|Single]] (14712x14989, 31.447MiB)