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{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/mips year_unknown foundry_tsmc tech_90nm}}

http://www.microchip.com/wwwproducts/Devices.aspx?product=PIC32MZ2048ECH100

Microchip PIC32 microcontroller.

  * 512 KB of SRAM
  * 2 MB of NOR flash
  * MIPS microAptiv CPU
  * No crypto accelerator (ECM series has this)
  * ADC
  * PLL
  * Other miscellaneous stuff

This is the first chip we've seen with a microAptiv core and Microchip's most powerful MCU to date, presumably intended to give STM32 a run for its money.

It's //brand new//, to the point that Microchip's website still shows it as "future product" and it's not sold on anything but dev boards. We just wanted process info so the rather serious errata were a non-issue.

Looks like a 90 nm copper process, probably 6-metal. Fill pattern looks like TSMC.

====== Box ======

{{:azonenberg:microchip:dscf5052_cropped.jpg?300|}} {{:azonenberg:microchip:dscf5053_cropped.jpg?300|}}{{:azonenberg:microchip:dscf5054_cropped.jpg?300|}} {{:azonenberg:microchip:dscf5055_cropped.jpg?300|}}

====== Board ======

{{:azonenberg:microchip:dscf5057_sm.jpg?600|}}

{{:azonenberg:microchip:dscf5056_sm.jpg?600|}}

====== Package ======

{{:azonenberg:microchip:dscf5059_cropped.jpg?300|}}

Markings:

    (Microchip logo) PIC32
    MZ2048ECH
    100-I/PT
    EAS3A3STDF3
    1347JEJ
        
====== Die ======

Size is approximately 5800 x 5500 μm (31.9 mm<sup>2</sup>)

===== Top layer =====

Overview

{{:azonenberg:microchip:pic32mz2048ech_bf_neo5x_4k.jpg?800|}}

Power distribution wiring

{{:azonenberg:microchip:pic32mz2048ech_30_bf_neo40x_annotated.jpg?600|}}

Top left corner showing standard TSMC fill patterns

{{:azonenberg:microchip:pic32mz2048ech_31_bf_neo20x_annotated.jpg?600|}}

Long shot of mask rev markings

{{:azonenberg:microchip:pic32mz2048ech_32_bf_neo20x_annotated.jpg?600|}}

Closeup of mask rev markings. Looks like five copper layers and one thick aluminum layer.

{{:azonenberg:microchip:pic32mz2048ech_33_bf_neo40x_annotated.jpg?600|}}

===== Active =====

NOR flash

{{:azonenberg:microchip:pic32mz2048ech100_01_se_35kx_5kv_15mm.jpg?600|}}

Litho-optimized SRAM cells. Bitcell area matches published TSMC 90nm SRAM size exactly.

{{:azonenberg:microchip:pic32mz2048ech100_02_se_10kx_5kv_15mm.jpg?600|}}

{{:azonenberg:microchip:pic32mz2048ech100_03_se_45kx_5kv_15mm.jpg?600|}}

Random gates in middle of die.

{{:azonenberg:microchip:pic32mz2048ech100_05_se_40kx_5kv_15mm.jpg?600|}}

{{:azonenberg:microchip:pic32mz2048ech100_07_se_1500x_5kv_15mm.jpg?600|}}