Silicon Pr0n

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[[vendor:xilinx|Xilinx]] XC9500XL CPLD family.

Made on a 350nm process by [[foundry:umc|UMC]] initially, fab moved to [[foundry:hejian|He Jian Technology Company]] later in the product life cycle (2005) (([[http://www.xilinx.com/support/documentation/customer_notices/xcn05015.pdf]])). 4 aluminum metal layers.

^ [[mcmaster:xilinx:xc9536xl|XC9536XL]] (4.38 mm<sup>2</sup>) ^ [[azonenberg:xilinx:xc9572xl|XC9572XL]] (7.27 mm<sup>2</sup>) ^ [[azonenberg:xilinx:xc95144xl|XC95144XL]] (13.16 mm<sup>2</sup>) ^ XC95288XL ^
| {{:vendor:xilinx:xc9536xl_ns50xu_small.jpg?154|}} \\ X8400 (rev A) | {{:azonenberg:xilinx:xc9572xl_bf_neo5x.jpg?224|}} \\ X8410 (rev A) | {{:azonenberg:xilinx:xc95144xl_bf_neo5x.jpg?365|}} \\ X8420 (rev A) | FIXME |

Thumbnail scale: 9 μm/pixel

One function block is 18 macrocells or "400 gates".