{{tag>collection_az vendor_xilinx type_logic type_logic/programmable type_logic/programmable/fpga year_unknown foundry_samsung tech_45nm}}

====== Package ======

144-pin TQFP supplied on cut tape. Die revision B.

Markings (top side):
  XILINX(R)
  SPARTAN(R)-6
  XC6SLX4(TM)
  TQG144BIV1209
  D4371643A
  2C

{{:azonenberg:xilinx:s7303126_cropped.jpg?300|}} {{:azonenberg:xilinx:s7303127_cropped.jpg?300|}} {{:azonenberg:xilinx:s7303128_cropped.jpg?300|}}

====== CAD floorplan ======

From PlanAhead.

{{:protected:azonenberg:xilinx:xc6slx4.png?300|}}

====== Die ======

Samsung 45nm process.

Passivation was somewhat damaged due to overly aggressive cleaning.

Overview

{{:azonenberg:xilinx:xc6slx4_bf_neo5x_2mp.jpg?600|}}

Bond pads and test points

{{:azonenberg:xilinx:xc6slx4_22_bf_neo20x_annotated.jpg?600|}}

Die logo

{{:azonenberg:xilinx:xc6slx4_23_bf_neo40x_annotated.jpg?600|}}

Damaged passivation (from cleaning)

{{:azonenberg:xilinx:xc6slx4_24_bf_neo40x_annotated.jpg?600|}}

x1 metal layer (probably M5 and M6) in SEM:

{{:azonenberg:xilinx:xc6slx4_01_se_20kv_27kx_21mm.jpg?600|}}

{{:azonenberg:xilinx:xc6slx4_02_se_20kv_8kx_21mm.jpg?600|}}

{{:azonenberg:xilinx:xc6slx4_03_se_20kv_40kx_21mm_annotated.png?600|}}

====== Map ======

[[http://siliconpr0n.org/map/xilinx/xc6slx4/mz_bf_neo5x/|Top metal @ neo5x]]