{{tag>collection_goodspeed vendor_ti type_unknown year_unknown foundry_unknown}}

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These photos are of a TMS32LC541B, (M) 1997 by Texas Instruments and
resold as part number AMBE2020 by DVSI.

According to the datasheet, it is mask programmed with 5K of SRAM and
28K of ROM.  8K of the ROM are independently wired and can be
connected to either the data or the instruction bus.

Looking at the die, we might guess the following regions.

1. A Texas Instruments logo in the center West of the chip.

2. The 28K-word x 16-bit ROM is implemented as fourteen 2K-word banks
   in seven pairs.  These are found in the West and Southwest,
   surrounding the model number.  One of these blocks can be
   reconfigured to be data rather than code, such as for a lookup
   table.  The ROM bits are visible from the surface, before
   delayering.

3. Five blocks of 1K-word x 126-bit DARAM are found in the North of
   the chip.

Page 21 of the datasheet describes a maskable option to protect the
contents of the on-chip memories.  When this is enabled, "no
externally originating instruction can access the on-chip memory
spaces.

Memory layout is on page 22.  The `MP/!MC` pin flips the chip between
Microprocess and Microcomputer modes.  When low, the internal ROM
appears at 0x9000.  When high, this region is external.  External
memory can be up to 64K of 16-bit words."
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====== Package ======

{{:goodspeed:ti:tms320lc541b:pack_top.jpg?300|}}

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{{:goodspeed:ti:tms320lc541b:pack_btm.jpg?300|}}

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====== Die ======

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[[https://siliconpr0n.org/map/ti/tms320lc541b/goodspeed_logo/|logo]]

  * [[https://siliconpr0n.org/map/ti/tms320lc541b/single/ti_tms320lc541b_goodspeed_logo.jpg|Single]] (7507x2151, 3.66022MiB)

[[https://siliconpr0n.org/map/ti/tms320lc541b/goodspeed_lowres/|lowres]]

  * [[https://siliconpr0n.org/map/ti/tms320lc541b/single/ti_tms320lc541b_goodspeed_lowres.jpg|Single]] (6655x6285, 17.5135MiB)