VAX-11/750 DC616 Scratchpad addressing gate array
This is a DEC chip and as such is known under multiple IDs:
Schematic : SPA Schematic : DC616C Package : 616C Package : 19-14690-00 Bill of Materials: 1914690-00
Built on the DC600 gate array, providing 400 4-input STTL NAND gates.
Technology specifications per EK-KA750-TD-002 (CPU Technical Description):
Implementation Technique - Gate Arrays
Circuit Technology - Low-Power Bipolar Schottky
Circuit Density - Large Scale Integration (LSI)
Die Size - .215 in x .244 in
Power Utilized per Die - 2 W max
Package Size - 1.44 in2 (2.4 in x 0.6 in)
I/O Circuits per Die - 44 I/O transceiver gates
Logic Gates - 400 identical 4-input NAND gates
Voltage Used - 2.5V, 5.0V
Speed per Gate - 5 - 10 ns
Package
616C 19-14690-00 66CE 3709-10 DEC 1 8435
The package is an odd pinless version of a 48-pin sidebraze CERDIP. In the machine the die faces towards the PCB and a heatsink is attached to the top of the package (facing the back of die).
