azonenberg:microchip:enc424j600
This is an old revision of the document!
10/100mbit SPI/parallel Ethernet controller.
Same 250 nm process technology as the PIC32MX series.
Package
44-pin QFN, decapped live.
Die
Rough stitch of old images with Am10x objective. Need to re-shoot at higher resolution.
Close-up of dense logic area at upper right:
Partial HF delayer of SRAM.
azonenberg/microchip/enc424j600.1395899319.txt.gz · Last modified: 2014/03/27 05:48 by azonenberg