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Chips
Processes
| Branded vendor | Branded ID | Process | Die ID |
|---|---|---|---|
CG24 / CG25 gate arrays
B4129AJ Tsutsuji Fujitsu CG24 Cell Library
Patent US4661815 describes the architecture and customization method for those chips. They're made of predefined i/o structures framing multiple columns of double CMOS transistor pairs called “Basic cells” (BC), spaced by empty columns for routing.
Customization is done by connecting the transistors with metal to form standard logic cells, which are then connected together and to the i/o structures.
- Red: input to cell.
- Green: output from cell.
All pictures are from 315-5674.
Input pin
Trace connects right behind the bonding pad.
Output pin
Trace connects to both N and P power transistors.
Bidirectional pin
One trace for input, and two individual traces for the N and P power transistors to allow tri-stating.
Output driver
Just a power inverter. Uses 3 BCs.
Bidirectional pin driver
Top input is output level, bottom input is enable. Outputs go to the pin structure transistors. Described page 10 of the MBCG25512 datasheet. Uses 5 BCs.
Inverter with 0.5 drive strength
Uses 0.5 BC.
Inverter with 1 drive strength
Uses 1 BC.
2NAND
Uses 1 BC.
