Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
process_tech [2015/12/17 22:49] – [Cheesing / bamboo structures] azonenbergprocess_tech [2015/12/17 22:52] (current) – [Eight or more layers] azonenberg
Line 90: Line 90:
 Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing. Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing.
  
-Example image (Xilinx XC6SLX4, 45nm Samsung process, probably ~12 layers). Top metal wires are massive, at least 5μm.+Example image (Xilinx XC6SLX4, 45nm Samsung process, layers). Top metal wires are massive, at least 5μm.
  
 {{:azonenberg:process_examples:topmetal_power.jpg?600|}} {{:azonenberg:process_examples:topmetal_power.jpg?600|}}
 
process_tech.txt · Last modified: 2015/12/17 22:52 by azonenberg
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution 4.0 International
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki