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gerlinsky:datatrak:s0089-1 [2022/01/22 03:38] – mcmastergerlinsky:datatrak:s0089-1 [2025/08/04 21:24] (current) – external edit 127.0.0.1
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-{{tag>collection_gerlinsky vendor_datatrak type_unknown year_unknown foundry_unknown}}+{{tag>collection_gerlinsky vendor_datatrak type_asic year_1988 foundry_ti}}
  
-Branded datatrak S0089-1, but fab by TI as CF30192+Branded datatrak S0089-1, but fab by TI as CF30192. 
 + 
 +Based on date and die markings, this appears to be a Texas Instruments TGC100 or similar gate array. 
 + 
 +Removed from a Datatrak "Mk.II" navigation receiver. Includes 68000 glue logic (address decode, DTACK, etc.) and a digital phase comparator. The phase comparator is used to receive phase-modulated data and measure the phase of the navigation bursts against a 20MHz TCXO built into the nav receiver.
  
  
Line 15: Line 19:
 </code> </code>
  
 +80-pin EIAJ-type (rectangular) PQFP package.
  
 ====== Die ====== ====== Die ======
  
 <code> <code>
-TI CF30192+(M) 1987 TI TGCX03 
 +(M) 1988 TI CF30192
 </code> </code>
  
-[[https://siliconpr0n.org/map/datatrak/s0089-1/mz_10x/|mz_10x]] 
  
-  * [[https://siliconpr0n.org/map/datatrak/s0089-1/single/datatrak_s0089-1_mz_10x.jpg|Single]] (23148x23123, 111.066MiB)+{{:gerlinsky:datatrak:s0089-1:bottomleft_20x.jpg?400|}}
  
-[[https://siliconpr0n.org/map/datatrak/s0089-1/mz_20x_scan1-cr_halfres/|mz_20x_scan1-cr_halfres]]+{{:gerlinsky:datatrak:s0089-1:topcorner_10x.jpg?400|}}
  
-  * [[https://siliconpr0n.org/map/datatrak/s0089-1/single/datatrak_s0089-1_mz_20x_scan1-cr_halfres.jpg|Single]] (18182x17595, 68.5258MiB)+{{:gerlinsky:datatrak:s0089-1:topcorner_20x.jpg?400|}}
  
-[[https://siliconpr0n.org/map/datatrak/s0089-1/mz_20x_scan1_halfres/|mz_20x_scan1_halfres]]+{{:gerlinsky:datatrak:s0089-1:topcorner_50x.jpg?400|}}
  
-  * [[https://siliconpr0n.org/map/datatrak/s0089-1/single/datatrak_s0089-1_mz_20x_scan1_halfres.jpg|Single]] (18228x17595, 69.0297MiB) 
  
-[[https://siliconpr0n.org/map/datatrak/s0089-1/mz_20x_scan2-cr_halfres/|mz_20x_scan2-cr_halfres]]+[[https://siliconprawn.org/map/datatrak/s0089-1/gerlinsky_mz_10x/|mz_10x]]
  
-  * [[https://siliconpr0n.org/map/datatrak/s0089-1/single/datatrak_s0089-1_mz_20x_scan2-cr_halfres.jpg|Single]] (18182x17595, 65.7236MiB)+  * [[https://siliconprawn.org/map/datatrak/s0089-1/single/datatrak_s0089-1_gerlinsky_mz_10x.jpg|Single]] (23148x23123, 111.066MiB)
  
-[[https://siliconpr0n.org/map/datatrak/s0089-1/mz_20x_scan2_halfres/|mz_20x_scan2_halfres]]+[[https://siliconprawn.org/map/datatrak/s0089-1/gerlinsky_mz_20x_scan1-cr_halfres/|mz_20x_scan1-cr_halfres]]
  
-  * [[https://siliconpr0n.org/map/datatrak/s0089-1/single/datatrak_s0089-1_mz_20x_scan2_halfres.jpg|Single]] (18182x17665, 66.1985MiB)+  * [[https://siliconprawn.org/map/datatrak/s0089-1/single/datatrak_s0089-1_gerlinsky_mz_20x_scan1-cr_halfres.jpg|Single]] (18182x17595, 68.5258MiB)
  
 +[[https://siliconprawn.org/map/datatrak/s0089-1/gerlinsky_mz_20x_scan1_halfres/|mz_20x_scan1_halfres]]
  
-====== Notes ======+  * [[https://siliconprawn.org/map/datatrak/s0089-1/single/datatrak_s0089-1_gerlinsky_mz_20x_scan1_halfres.jpg|Single]] (18228x17595, 69.0297MiB)
  
-<code> +[[https://siliconprawn.org/map/datatrak/s0089-1/gerlinsky_mz_20x_scan2-cr_halfres/|mz_20x_scan2-cr_halfres]]
-Imgur link: http://imgur.com/a/Kfy7g+
  
 +  * [[https://siliconprawn.org/map/datatrak/s0089-1/single/datatrak_s0089-1_gerlinsky_mz_20x_scan2-cr_halfres.jpg|Single]] (18182x17595, 65.7236MiB)
  
-Probably a TI TGT2000 gate array. 84 pin EIAJ QFP.+[[https://siliconprawn.org/map/datatrak/s0089-1/gerlinsky_mz_20x_scan2_halfres/|mz_20x_scan2_halfres]]
  
-Geometry 0.5 mic, per: +  * [[https://siliconprawn.org/map/datatrak/s0089-1/single/datatrak_s0089-1_gerlinsky_mz_20x_scan2_halfres.jpg|Single]] (18182x17665, 66.1985MiB)
-https://books.google.co.uk/books?id=br3gBwAAQBAJ&lpg=PA403&dq=TGT2000%20gate%20array&pg=PA403#v=onepage&q=TGT2000%20gate%20array&f=false +
- The Electronic Design Automation Handbook +
- Dirk Jansen +
- page 403+
  
  
-Gate array - also known as "Embedded Array"+xcf: https://siliconprawn.org/map/datatrak/s0089-1/single/datatrak_s0089-1_gerlinsky_10x_20x_composite.xcf
  
-Some support in LeonardoSpectrum for TI TGC2000 embedded arrays: 
- https://www.mentor.com/products/fpga/synthesis/partners/asic/texas_instruments 
- http://www.datasheetarchive.com/files/texas-instruments/sc/docs/asic/gate/tgc2000.htm 
- mentions Cadence, Mentor and Synopsys 
- 
-http://smithsonianchips.si.edu/ice/cd/ASIC98/SECTION7.PDF 
-http://smithsonianchips.si.edu/ 
- 
-ieeexplore.ieee.org/document/208717/ 
-http://ieeexplore.ieee.org/document/216013/ 
- 
- 
-https://books.google.co.uk/books?id=GzPpAAAAIAAJ&lpg=PA53&dq=Texas%20Instruments%20TAHC%20gate%20arrays&pg=PA56#v=onepage&q=Texas%20Instruments%20TAHC%20gate%20arrays&f=false 
- "The design of CMOS gate arrays as student undergraduate projects" 
- McGinnity T. M, et al 
- Department of Physics, University College of Wales, Aberystwyth 
- (pub. in Electronics Computer Aided Design - ed: Jones and Buckley) 
- Shows example routed layout for TAHC10 GA 
- 
-https://docslide.net/documents/gate-array-architectures.html 
- 
- 
-Relevant patents: 
- 
-http://www.google.co.uk/patents/US5656834 
- 
-https://www.google.co.uk/patents/US5106773?dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEIfDAM 
- 
-https://www.google.co.uk/patents/EP0662716A2?cl=en&dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEIkQEwDw 
- 
-https://www.google.co.uk/patents/US5939740?dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEImAEwEA 
- Sheet 22,24 - similar to the base cell on the ASIC 
- 
-https://www.google.co.uk/patents/US5479034?dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEInwEwEQ 
- Sheet 24 looks almost exactly like the base cell 
- 
-https://www.google.co.uk/patents/US5574298?dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEIZzAJ 
- 
-https://www.google.co.uk/patents/US5502404?dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEIbjAK 
- 
-https://www.google.co.uk/patents/US5652441?dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwj-uZSV-4fWAhUSLlAKHbEtA-YQ6AEIRDAE 
-https://patentimages.storage.googleapis.com/pages/US5652441-1.png 
-https://patentimages.storage.googleapis.com/pages/US5652441-2.png 
- ^^^ Cell looks almost identical 
- 
-https://www.google.co.uk/patents/US5217915 
- 
-https://www.google.co.uk/patents/US5275962 
- 
-https://www.google.co.uk/patents/US5422581?dq=inassignee:%22texas+instruments%22+%22gate+array%22+%22cell%22+-FPGA&hl=en&sa=X&ved=0ahUKEwi1pYKJj6HWAhXGL1AKHTaGAOQQ6AEIKDAA 
-https://www.google.co.uk/patents/US5502404?dq=inassignee:%22texas+instruments%22+%22gate+array%22+%22cell%22+-FPGA&hl=en&sa=X&ved=0ahUKEwi1pYKJj6HWAhXGL1AKHTaGAOQQ6AEILzAB 
- 
-https://www.google.co.uk/patents/EP0683524B1?cl=en&dq=inassignee:%22texas+instruments%22+%22gate+array%22&hl=en&sa=X&ved=0ahUKEwjxg-zCjqHWAhVMJVAKHcT-DpQQ6AEIlAMwNA 
- 
-https://www.google.co.uk/search?num=100&safe=active&hl=en&biw=1918&bih=933&tbm=pts&q=inassignee%3A%22texas+instruments%22+%22gate+array%22+%22cell%22+-FPGA&oq=inassignee%3A%22texas+instruments%22+%22gate+array%22+%22cell%22+-FPGA&gs_l=psy-ab.3...1505.4044.0.4234.15.14.1.0.0.0.126.978.12j2.14.0....0...1.1.64.psy-ab..0.0.0.cNdcDaKOZNU 
- 
-https://www.cl.cam.ac.uk/teaching/2000/VLSI/local/VLSI.pdf 
- 
- 
-http://www.degate.org/ 
- 
-http://www.degate.org/documentation/ 
-</code> 
gerlinsky/datatrak/s0089-1.1642822712.txt.gz · Last modified: 2022/01/22 03:38 by mcmaster