Differences

This shows you the differences between two versions of the page.

--- fet [2016/01/03 07:42] – [MOS 6522] mcmaster
+++ fet [2016/01/03 08:02] (current) – [Xilinx XC2018] mcmaster
@@ Line 37: / Line 37: @@
 ====== Examples ======
-===== Gate: early metal =====
+===== Gate: poly =====
-==== MOS MPS7083 ====
+==== RSA SecurID 1C ====
-{{:mcmaster:mos:mps7083:q_mz.jpg?300}}
+{{:mcmaster:n_fet_no_metal.png?100}}
-{{:mcmaster:mos:mps7083:q_dlyr1.jpg?300}}
+Some of contact metal can be seen on the bottom but the gate itself is poly.  The [[:cmos|CMOS page]] details its use in an inverter
-Above top: top metal.  Bottom: Al and some SiO2 removed w/ SiO2 thin film interference showing oxide thickness
-Typical metal gate CMOS transistor as used in non-trivial chips (ie CPU).  The gate driver comes in on the right through an active area.  The SiO2 has a cutout to allow placing a (Al?) via up to M1.
+==== Xilinx XC2018 ====
-M1 goes left where it meets an active area.  The teal SiO2 M1 area has thick oxide that prevents it from coupling to the Si below.  However, the dark blue cutout brings it much closer (but not contacting, ie an "isolated gate" FET) such that its able to induce charge into the substrate below.  Therefore, while metal crosses several active regions only one transistor is formed.
+{{:mcmaster:xilinx:xc2018:q.jpg?150|}}
-While the metal does spill over to some adjacent areas there are several things that prevent them from becoming an effective transistor:
+Similar process to the SecurID.  Left middle has a via to poly.  The poly extends right over an active area to form a transistor.  The active area has contacts at top and bottom.
-    * They do not fully cut off active areas
-    * These areas are likely biased such that adding additional charge wouldn't do anything
-==== Fairchild CD4011 ====
+==== MOS 6522 ====
-{{:image:fairchild_4011_transistor.jpg?300}}
+{{:mcmaster:mos:6522:q.jpg?150|}}
-{{:image:cmos_metal_gate_transistor_no_metal.jpg?300}}
+Above: delayered showing poly (textured orange), active (orange), and buried contact (shadow)
-Above top: original transistor.  Bottom: very siimlar delayered transistor
+The top polysilicon connects is driven by a via at top left.  It crosses the active area to the right to form a transistor.
-These textbook style metal gate transistors are rare in real devices.  They are similar to the preceeding MOS transistor with cutouts for both the gate and vias.  However, the doping is very different.  The areas immediately to the left and right of the transistor must be opposite doping to the center and surrounging area (which apper to be doped the same per the delayer image).  The via features are due to ohmic contact / windowing.  I'm guessing the green layer is the opposite doping ie N if the center is P) and the layers on either side of it  are the same doping based on thin film interference color.  However, I'm still unclera why there are three different main regions.
+The bottom transistor side connects directly from active to poly via a buried contact.  This poly goes off to bottom left to drive another transistor.
-Consider staining these to get more info.
-===== Gate: poly =====
+==== MOS 6526 ====
-==== RSA SecurID 1C ====
+{{:mcmaster:mos:6526:q.jpg|}}
-{{gallery>:mcmaster:n_fet_no_metal.png}}
+Above: top metal image
-Some of contact metal can be seen on the bottom but the gate itself is poly.  The [[:cmos|CMOS page]] details its use in an inverter
+Active area enters lower left and meets poly at a buried contact.  The poly sweeps right to up to form a transistor separating the via from the active area at the right of the image.
+==== CMOS quiz ====
+{{:quiz:metal_gate_cmos:q.jpg?300}}
-==== MOS 6522 ====
+[[:quiz:3h7e0f4|See quiz]] for analysis
-{{:mcmaster:mos:6522:q.jpg?300|}}
-Above: delayered showing poly (textured orange), active (orange), and buried contact (shadow)
+===== Gate: early metal =====
-The top polysilicon connects is driven by a via at top left.  It crosses the active area to the right to form a transistor.
+==== MOS MPS7083 ====
-The bottom transistor side connects directly from active to poly via a buried contact.  This poly goes off to bottom left to drive another transistor.
+{{:mcmaster:mos:mps7083:q_mz.jpg?150}}
+{{:mcmaster:mos:mps7083:q_dlyr1.jpg?150}}
-==== MOS 6526 ====
+Above top: top metal.  Bottom: Al and some SiO2 removed w/ SiO2 thin film interference showing oxide thickness
-{{:mcmaster:mos:6526:q.jpg?300|}}
+Typical metal gate CMOS transistor as used in non-trivial chips (ie CPU).  The gate driver comes in on the right through an active area.  The SiO2 has a cutout to allow placing a (Al?) via up to M1.
-Above: top metal image
+M1 goes left where it meets an active area.  The teal SiO2 M1 area has thick oxide that prevents it from coupling to the Si below.  However, the dark blue cutout brings it much closer (but not contacting, ie an "isolated gate" FET) such that its able to induce charge into the substrate below.  Therefore, while metal crosses several active regions only one transistor is formed.
-Active area enters lower left and meets poly at a buried contact.  The poly sweeps right to up to form a transistor separating the via from the active area at the right of the image.
+While the metal does spill over to some adjacent areas there are several things that prevent them from becoming an effective transistor:
-==== CMOS quiz ====
-{{:quiz:metal_gate_cmos:q.jpg?300}}
+    * They do not fully cut off active areas
+    * These areas are likely biased such that adding additional charge wouldn't do anything
+==== Fairchild CD4011 ====
+{{:image:fairchild_4011_transistor.jpg?150}}
+{{:image:cmos_metal_gate_transistor_no_metal.jpg?150}}
+Above top: original transistor.  Bottom: very siimlar delayered transistor
+These textbook style metal gate transistors are rare in real devices.  They are similar to the preceeding MOS transistor with cutouts for both the gate and vias.  However, the doping is very different.  The areas immediately to the left and right of the transistor must be opposite doping to the center and surrounging area (which apper to be doped the same per the delayer image).  The via features are due to ohmic contact / windowing.  I'm guessing the green layer is the opposite doping ie N if the center is P) and the layers on either side of it  are the same doping based on thin film interference color.  However, I'm still unclera why there are three different main regions.
+Consider staining these to get more info.
-[[:quiz:3h7e0f4|See quiz]] for analysis
 ====== References ======