Differences

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--- manufacture [2012/08/13 05:51] – [Printing the photomask] mcmaster
+++ manufacture [2013/10/20 14:59] (current) – external edit 127.0.0.1
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 ====== Obtaining silicon ======
-Must be highly purified.  Most Si goes to the steel industry with <10% going to making wafers. [Wiki: Si]
+Most Si goes to the steel industry with <10% going to making wafers. [Wiki: Si]
+FIXME: what does Si ore look like?
 ====== Making ingots ======
-Melted in high temp furnace. A seed crystal is dropped in and forms a large crystal.  Chemicals are added to give p or n doping.
+Silicon must be highly purified for use in semiconductors.  Its melted in high temp furnace with several variations on how to purify it based on whether cost or purity (quality) is a higher concern.  Chemicals are added to give p or n doping.
+FIXME: steal a picture from Wiki or something
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 Programs like Cadence VLSI, Magic VLSI, and others are used to design a circuit and produce CAD files.
+FIXME: put a magic screenshot
 ====== Printing the photomask ======
@@ Line 28: / Line 33: @@
 ====== Printing the wafer ======
+{{:manufacture:dec_57-19400-04_registration.png?300|}}
 There are two different methods: contact and w/e the other one is called. In the contact method, the plate and wafer are pressed together. This results in low separation, meaning cleaner print. However, the ever so expensive photomask will wear out sooner. In the other method the photomask is above. One or more complete IC layers will be on the photomask. If necessary, a stepper will move the mask around to print as many repetitions as will fit on the wafer.
-Each time a layer is added, it must be aligned to previous layers. It seems layer misalignment is responsible for many failed wafers.
+Each time a layer is added, it must be aligned to previous layers. It seems layer misalignment is responsible for many failed wafers.  Above shows some registration marks on the wafer to make aligning layers easier (DEC 57-19400-04, left chip).
 ====== Wafer testing ======
-Some circuits can undergo basic testing.by using test pads when still in the wafer. This eliminates the following steps only to find the entire wafer was bad. If too many units are bad during initial testing, the whole process is typically aborted.
+{{:manufacture:blue_tak_top_angled.jpg?300|}}
+{{:manufacture:blue_tak_top.jpg?300|}}
+Some circuits can undergo basic testing.by using test pads when still in the wafer. This eliminates the following steps only to find the entire wafer was bad. If too many units are bad during initial testing, the whole process is typically aborted.  Each bad IC is marked with a dot of black ink.  Above is from the same wafer as in the next section.
+FIXME: get a picture of a probe card (off of my phone...)
+FIXME: add probe scrube marks
 ====== Dicing ======
-Diamond saws cut the wafer into individual dies. They are then punched out and collected.
+{{:manufacture:blue_tak_remaining.jpg?300|}}
+{{:manufacture:blue_tak_side.jpg?300|}}
+Wafers are placed on a sticky mat, often blue, and then cut with diamond saws into individual dies.  The saws are precisely positioned to be just into the plastic layer.  The non-dotted (good) dies are then collected.  See first photo for an example (unknown device, probably a power diode).  Only the dotted (bad) dies remain.  The second photo shows the side of the wafer where the depressions between dies ends just where the wafer ends.  Also note the punch marks where good dies were ejected.
+{{:manufacture:diced_wafer.jpg?300|}}
+Alternatively, smaller research runs are sometimes scribed (thin surface cut) and then snapped.  This is less accurate and safe but requires less equipment and setup.  Second photo was scribed and notice how not everything is broken, chips slightly vary and size, and some are even broken from a bad snap.
 ====== Bonding and early packaging ======