quiz:metal_gate_cmos_logic_data
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quiz:metal_gate_cmos_logic_data [2012/05/24 01:34] – created mcmaster | quiz:metal_gate_cmos_logic_data [2016/01/03 04:18] (current) – removed mcmaster | ||
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- | ====== Inputs and outputs ====== | ||
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- | With the entire chip perimeter characterized we can start analyzing the logic. | ||
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- | * Basic logic chips are often regular with a few circuits repeated abeit in a very custom layout. | ||
- | * Detail | ||
- | * {{: | ||
- | * Exclude ESD protection | ||
- | * Isolated meaning that you could form N truth tables because parts of circuits do not affect others | ||
- | * Hint: think about input : output ratio and repeated layout | ||
- | - 1 | ||
- | - 2 | ||
- | - 3 | ||
- | - 6 | ||
- | - 9 | ||
- | * [3] | ||
- | * (1) | ||
- | * Using our earlier analysis we have 9 inputs and 3 outputs. | ||
- | * {{: | ||
quiz/metal_gate_cmos_logic_data.1337823293.txt.gz · Last modified: 2013/10/20 14:59 (external edit)