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--- resistor [2012/07/01 21:50] – mcmaster
+++ resistor [2013/10/20 14:59] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
-====== Always on transistor ======
+====== Depletion load ======
-These are arranged with the transistor tied to be always on.  A MOSFET is classified into 3 areas of operation:
+FIXME: compare with analysis at [NMOS logic design], tried to do for enhancement mode and so analysis didn't work out
-  * Cutoff (VGS < Vth): little conduction
-  * Triode (VGS > Vth and VDS < (VGS - Vth)): resistive
-  * Saturation (VGS > Vth and VDS > (VGS - Vth)): conductive
-Pulldown PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://www.4004.com):
+Most MOSFETs encountered are enhancement.  In essence a its off if you don't apply any voltage between gate and source and fully on if you apply lots of voltage between drain and source and a little between the gate and source (ie switching a high voltage load).  However, there are also depletion mode transistor which have essentially the opposite behavior: they are normally on with VGS = 0.
+Depletion load PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://www.4004.com):
 {{:flylogic:intel_400:pullup_metal_flylogic.png}}
@@ Line 18: / Line 17: @@
 {{:mcmaster:resistor:pmos_pulldown_sch.png}}
-(FIXME: look into analysis. The metal is VDD (-10V). For PMOS, cutoff occurs when VGS > Vth and assume Vth = -3V or something like that.  If VGS is 0 the resistor does nothing as there is no potential difference.  Now note that since VG = VD and so VGS = VDS)
+So the natural question to ask is how do you tell a depletion from an enhancement load MOSFET?  For a non-obfuscated digital design typically only depletion mode transistors have this configuration and are enhancement otherwise.  Like this, once you get into analog all bets are off and you need to be careful.
@@ Line 58: / Line 57: @@
   - Resistor Fabrication on Semiconductor Wafers: http://www.siliconfareast.com/resistor-fab.htm
   - http://uvicrec.blogspot.com/2011/09/understanding-intel-4004.html
+  - NMOS logic design: http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_4_NMOS_Logic_Design_package.pdf