Differences

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--- azonenberg:xilinx:xc3s50a [2014/02/05 04:21] – azonenberg
+++ azonenberg:xilinx:xc3s50a [2015/01/04 22:50] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
 {{tag>collection_az vendor_xilinx year_2006 type_logic type_logic/programmable type_logic/programmable/fpga foundry_ibm foundry_umc tech_90nm}}
-See also: [[protected:mcmaster:xilinx:xc3s50a]]
+See also: [[mcmaster:xilinx:xc3s50a]]
 ====== Package ======
@@ Line 10: / Line 10: @@
 ====== Die ======
+Size is approximately 3200 x 2850 μm (9.12 mm<sup>2</sup>)
+===== M8 with intact passivation =====
 {{:azonenberg:xilinx:xc3s50a_bf_neo5x.jpg?600|}}
+{{:azonenberg:xilinx:xc3s50a_07_bf_neo20x_annotated.jpg?600|}}
 {{:azonenberg:xilinx:xc3s50a_08_bf_neo20x_annotated.jpg?600|}}
@@ Line 24: / Line 30: @@
 {{:azonenberg:xilinx:xc3s50a_13_bf_neo40x_annotated.jpg?600|}}
+===== M8 with passivation removed =====
+{{:azonenberg:xilinx:xc3s50a:xc3s50a_m8_bf_neo5x_3k.jpg?600|}}
+===== M7 =====
+{{:azonenberg:xilinx:xc3s50a:xc3s50a_m7_bf_neo5x_3k.jpg?600|}}
+M6 and below could not be revealed cleanly with HF etching, need to CMP another die.
+===== Active =====
+{{:azonenberg:xilinx:xc3s50a:xc3s50a_active_bf_neo10x_3k.jpg?600|}}
+Might be some poly too.
+Left side of block RAM
+{{:azonenberg:xilinx:xc3s50a:xc3s50a_active_30_bf_neo40x_annotated.jpg?600|}}
+Gap between two groups of CLBs
+{{:azonenberg:xilinx:xc3s50a:xc3s50a_active_31_bf_neo40x_annotated.jpg?600|}}