Differences

This shows you the differences between two versions of the page.

--- linksys:lne100tx [2013/01/23 21:09] – azonenberg
+++ linksys:lne100tx [2015/11/11 21:56] (current) – azonenberg
@@ Line 1: / Line 1: @@
-{{tag>collection_az}}
+{{tag>collection_az vendor_linksys vendor_adhoc year_1999 type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet tech_unknown foundry_unknown}}
-{{tag>vendor_linksys}}
-{{tag>vendor_adhoc}}
-{{tag>type_interface}}
-{{tag>type_interface_serdes}}
-{{tag>type_interface_serdes_ethernet}}
-{{tag>type_network}}
-{{tag>type_network_ethernet}}
 ====== Overview ======
-Appears to be a rebadged Adhoc Technologies AH101. This is apparently an OEM part with very little discussion in the literature, see [[http://scripts.online.ru/it/news/engnews/98/11/23_009.htm]].
+Appears to be a rebadged Adhoc Technologies AH101. This is apparently an OEM part with very little discussion in the literature, see [[http://scripts.online.ru/it/news/engnews/98/11/23_009.htm|http://scripts.online.ru/it/news/engnews/98/11/23_009.htm]].
-Seems to be a 3-metal ~350nm copper process.
+[[http://www.eetimes.com/document.asp?doc_id=1119759|http://www.eetimes.com/document.asp?doc_id=1119759]]
+Seems to be a 3-metal ~350nm process.
 ====== Board photo (from Newegg) ======
-{{http://images10.newegg.com/NeweggImage/productimage/33-124-107-16.jpg}}
+{{http://images10.newegg.com/NeweggImage/productimage/33-124-107-16.jpg?direct&}}
 ====== Die pics ======
@@ Line 22: / Line 17: @@
 Die label
-{{:azonenberg:linksys:lne100tx_11_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_11_bf_neo40x_annotated.jpg?600}}
 Mask revision labels
-{{:azonenberg:linksys:lne100tx_01_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_01_bf_neo40x_annotated.jpg?600}}
 Bond pads
-{{:azonenberg:linksys:lne100tx_04_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_04_bf_neo40x_annotated.jpg?600}}
 Overview of upper right corner of die, showing power busing and part of the PHY.
-{{:azonenberg:linksys:lne100tx_05_bf_neo5x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_05_bf_neo5x_annotated.jpg?600}}
 Buffer memory and some logic.
-{{:azonenberg:linksys:lne100tx_06_bf_neo5x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_06_bf_neo5x_annotated.jpg?600}}
 Lower left corner. Small memory array (EEPROM maybe?) and logic.
-{{:azonenberg:linksys:lne100tx_07_bf_neo5x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_07_bf_neo5x_annotated.jpg?600}}
 Upper center.
-{{:azonenberg:linksys:lne100tx_10_bf_neo5x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_10_bf_neo5x_annotated.jpg?600}}
 Close up of cell array.
-{{:azonenberg:linksys:lne100tx_08_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_08_bf_neo40x_annotated.jpg?600}}
-{{:azonenberg:linksys:lne100tx_09_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:linksys:lne100tx_09_bf_neo40x_annotated.jpg?600}}