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Table of Contents
Microchip PIC32 microcontroller.
* 32 KB of SRAM * 512 KB of NOR flash * MIPS M4K CPU * ADC * PLL * Other miscellaneous stuff
Package
Markings:
(Microchip logo) PIC32MX340F 512H-80I/MR (e3) 0850KGV
Die
Size is approximately 4280 x 4740 μm (20.29 mm2).
Looks to be a 4-metal ~220 nm process.
M4 (top layer)
Overview
Interesting region in the middle of the die. Not sure what it does but provides a nice view of standard cells on lower layers.
Test points on the flash array. Probably tied to bit/word lines. Maybe used for measuring read/erase margins during characterization?
Random wiring in the middle of the die with test points
Mask rev markings
Test patterns on bottom edge
Delayering (HF)
Power busing near flash with exposed vias. ~700 nm via pitch is consistent with the 220-250 nm process node.
M1
Overview
Top left corner of SRAM array
Edge of flash array
Random standard cell region. Note large number of dummy cells. This is most likely due to their use of a cost-optimized process with less metal layers than would be necessary to route the design with more densely packed cells.
