• 28 nm
• 40 nm
• 65 nm
• 90 nm
• 0.13 um
• 0.15 um
• 0.18 um
• 0.25 um
• 0.35 um
• 0.5 um
• 0.6 um
• 8“ wafers

Mostly copper with thick aluminum on the top layer.

1.8V core with I/O up to 3.3V. Many mixed-signal devices will have an on-die LDO for generating 1.8 from 3.3 however higher end devices such as programmable logic typically expect an external 1.8V supply.

4-5 aluminum layers with tungsten vias, titanium-based barrier metal, and cobalt silicide contacts.

Partial design rules and FIB sections at http://siliconexposed.blogspot.com/2014/02/process-overview-umc-180nm-envm.html

Power ring and pad layouts can vary somewhat, as does presence or absence of CMP filler between bond pads.

The CMP filler pattern is distinctive and can be used as positive ID.

CMP fill pattern table (measured from XC2C32A)