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--- quiz:metal_gate_cmos_io_data [2012/05/24 01:06] – created mcmaster
+++ quiz:metal_gate_cmos_io_data [2016/01/03 04:20] (current) – removed mcmaster
@@ Line 1: / Line 1: @@
-====== Inputs and outputs ======
-In the previous module you came up with the pin numbering scheme and identified power and ground.  Now we'll go a little deeper to figure out data flow.
-  * Identity the circle containing ESD protection
-    * Detail
-      * {{:quiz:metal_gate_cmos:esd_q.jpg?600|}}
-    - A
-    - B
-    - C
-    - D
-    - E
-    * [1]
-    * (1)
-    * Many chips use large parallel diodes for ESD protection and so this ones a little different.  However, ESD protection can often be identified by virtue of a component that attaches to both VDD and VSS.  While some of the transistors do this, they have logical connections that indicate they have a higher purpose.  ESD protection on the other hand tends to be very simple and regular.  Looking at the components in A I believe they are resistors as seen with NMOS logic (ex: see Intel 4004 die photos and Flylogic analysis).  Presumably this provides a more favorable conductive path and shunts away from the input gates.
-      * B is a transistor
-      * C is a transistor
-      * D is a bond wire (ball bond)
-      * E just has more metal and metal doesn't typically help ESD.  It can on larger chips when its used as a capacitor between VDD and VSS