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process_tech [2013/01/16 17:53] – [Cheesing / bamboo structures] azonenbergprocess_tech [2015/12/17 22:52] (current) – [Eight or more layers] azonenberg
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 ===== Cheesing / bamboo structures ===== ===== Cheesing / bamboo structures =====
  
-Copper processes will typically include "cheesing" or a "bamboo structure" - small rectangular cutouts in large power buses - because copper is more susceptible to electromigration than aluminum is. (see [[http://en.wikipedia.org/wiki/Electromigration#Bamboo_structure_and_metal_slotting|Wikipedia article on electromigration]]) because copper is more susceptible to electromigration. Since mass transport in electromigration typically occurs parallel to grain boundaries, the rate of mass transport can be dramatically reduced by making the wire width smaller than the grain size so that grain boundaries are largely perpendicular to the direction of current flow. As a result, the presence of these structures can be used as a very strong hint that the process is copper based.+Modern processes will typically include "cheesing" or a "bamboo structure" - small rectangular cutouts in large power buses (see [[http://en.wikipedia.org/wiki/Electromigration#Bamboo_structure_and_metal_slotting|Wikipedia article on electromigration]]). Since mass transport in electromigration typically occurs parallel to grain boundaries, the rate of mass transport can be dramatically reduced by making the wire width smaller than the grain size so that grain boundaries are largely perpendicular to the direction of current flow. As a result, the presence of these structures can be used as a hint that the trace in question carries high current.
  
-Xilinx CoolRunner-II CPLD (180nm copper, probably 7 metal layers)+Xilinx CoolRunner-II CPLD (180nm aluminum, 4 metal layers)
  
 {{::azonenberg:process_examples:copper_power_rail.jpg?400|}} {{::azonenberg:process_examples:copper_power_rail.jpg?400|}}
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 ===== Single layer ===== ===== Single layer =====
  
-Very simple chips have only one metal layer and (usually) one polysilicon layer. These are normally very simple devices like 7400-series logic up to i4004 era and are largely hand laid out, as standard logic cells are infeasible in such a process. Geometry is greater than 5 μm in most cases. Almost always nonplanar.+Very simple chips have only one metal layer and (usually) one polysilicon layer. These are normally very simple devices like 7400-series logic up to i4004 era and are largely hand laid out, as standard logic cells are infeasible in such a process. Geometry is greater than 5 μm in most cases. Almost always nonplanarized.
  
 FIXME: get a photo FIXME: get a photo
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 ===== Two layers ===== ===== Two layers =====
  
-Large geometry (>500nm), and nonplanar.+Large geometry (>500nm), and nonplanarized.
  
 Standard cells are commonly used in 2-metal processes, with large gaps between individual rows of cells. Horizontal routing runs between rows of cells on M1 (M1 on top of the cells is used by the cell library and for power routing) and vertical routing runs on top of both on M2. Standard cells are commonly used in 2-metal processes, with large gaps between individual rows of cells. Horizontal routing runs between rows of cells on M1 (M1 on top of the cells is used by the cell library and for power routing) and vertical routing runs on top of both on M2.
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 {{:azonenberg:process_examples:3metal.jpg?600|}} {{:azonenberg:process_examples:3metal.jpg?600|}}
  
-===== Five and seven layers =====+===== Four to seven layers =====
  
-Feature sizes range from 250 to 180nm.+Feature sizes range from 350 to 180nm.
  
 Typically one layer for cells and two or three interconnect layers in each direction. Power distribution is similar to 3-metal designs. Typically one layer for cells and two or three interconnect layers in each direction. Power distribution is similar to 3-metal designs.
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 {{:azonenberg:process_examples:5metal.jpg?600|}} {{:azonenberg:process_examples:5metal.jpg?600|}}
 +
 +TODO: Cross section example
  
 ===== Eight or more layers ===== ===== Eight or more layers =====
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 Feature sizes are 130nm and below. Feature sizes are 130nm and below.
  
-Many dense interconnect layers, as with 5/7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing.+Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing.
  
-Example image (Xilinx XC6SLX4, 45nm Samsung process, probably ~12 layers). Top metal wires are massive, at least 5μm.+Example image (Xilinx XC6SLX4, 45nm Samsung process, 9 layers). Top metal wires are massive, at least 5μm.
  
 {{:azonenberg:process_examples:topmetal_power.jpg?600|}} {{:azonenberg:process_examples:topmetal_power.jpg?600|}}
  
 +
 +====== Typical layer dimensions ======
 +
 +This section prepared initially to better understand typical layer thickness to understand how to improve wet etching processes and to better understand limitations of lapping.
 +
 +
 +===== Bipolar =====
 +
 +
 +===== NMOS/PMOS =====
 +
 +
 +===== CMOS =====
 +
 +Samsung KM44C4000J-7 16 Megabit DRAM, Report Number: SCA 9311-300I vertical dimensions:
 +  * Die thickness: 0.3 mm
 +  * Die coat: 9.5 um
 +    * Die coat: "A patterned (to clear bond pads) polyimide die coat was present to protect against alpha particle-induced leakage. Coverage was good."
 +  * Passivation 3: 0.55 um
 +  * Passivation 2: 0.3 um
 +  * Passivation 1: 0.1 um
 +  * M2 (Al): 0.9 um
 +  * Glass 3 ILD: 0.4 um
 +  * Glass 2 ILD: 0.4 um
 +  * Glass 1 ILD: ~0.08 um
 +  * M1 cap: 0.04 um
 +  * M1 (Al): 0.55 um
 +  * M1 barrier: 0.15 um
 +  * Intermediate glass 2: 0.5 um
 +  * Polycide-silicide: 0.2 um
 +  * Polycide-silicide poly 4: ~0.05 um
 +  * Intermediate glass 1: 0.2 um
 +  * Oxide on poly 3: 0.1 um
 +  * Poly 3: 0.1 um
 +  * Capacitor dielectric: ~0.015 um
 +  * Poly 2: 0.15 um
 +  * Interpoly oxide total: 0.35 um
 +  * Interpoly oxide nitride: ~0.04 um
 +  * Poly 1: 0.2 um
 +  * Local oxide (under poly 1): 0.3 um
 +  * Oxide on N+: ~0.08 um
 +  * Oxide on P+: ~0.06 um
 +  * N+ source/drain: 0.2 um
 +  * P+ source/drain: 0.3 um
 +  * (likely) N-well: 4.5 um
 +
 +
 +[Interconnect Scaling] says that ITRS '99 "dictated dimensions" for the '99 technology node are:
 +  * 0.18 um process
 +  * Global (ie long) height: ~1.16 um
 +  * Semiglobal height: ~0.64 um
 +  * Local height: ~0.36 um
 +
 +TODO: Add extracted design rules from XC2C32A
 +
 +==== Thick metal process ====
 +
 +[Thick Metal] has:
 +  * 0.8 um process
 +  * Intended use: maybe RF ICs
 +  * Inter-Metal Dielectric (IMD) thickness: 1.1 um
 +  * Metal thickness: 2.1 um or 2.1 um
 +
 +===== BiCMOS =====
 +
 +
 +====== References ======
 +
 +  * Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs ("Thick Metal", aka we luv long titles): http://etrij.etri.re.kr/pdfdata/21-04-01.pdf
 +  * Interconnect Scaling: http://www.stanford.edu/class/ee311/NOTES/Interconnect%20Scaling.pdf
process_tech.1358358824.txt.gz · Last modified: 2013/10/20 14:59 (external edit)