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The intention of this table is to allow rough identification of a device's technology node.

This list includes ITRS standard nodes only, tag devices at the nearest appropriate node. Please only tag devices whose process geometry is known for certain; this will allow us to more easily compare examples of devices at each node.

Devices ≤ 90nm typically have thick top metal with a much larger design rule. There do not appear to be significant scaling trends in top metal pitch below 90nm,

There are two Vcore columns. The typical numbers are the nominal operating voltages for standard process, the minimum numbers are the lowest voltages allowed for low-power versions of the process.

Node	Vcore (min)	Vcore(typ)	Layer count	Mz pitch	M1 pitch	SRAM cell size	Notes
Unknown		N/A	N/A
Huge (>10 µm)		>= 5
10 µm
3 µm
1500 nm
1000 nm	2.5	3.3 - 5.0	2
800 nm	2.5	5.0	2
600 nm		5.0	2 - 3
350 nm	2.0	3.3 - 5	3 - 5	1700 nm	1525 nm	46.17 µm2 (6T)	EPM3064A, PIC12F683
250 / 220 nm		1.8 - 3.3	4 - 5
180 / 150 nm		1.5 - 1.8	4 - 6	1000 - 1550 nm	565 nm	4.15 µm2 (6T)	XC2C32A, KSZ9021RN, PIC32MX340F512H
130 / 110 nm		1.5 - 1.8	5 - 8	3200 nm		2.91 µm2 (6T)	CY8C4245AXI
90 nm	1.14	1.2	7 - 10	15000 nm		3.92 µm2 (8T) , 0.86 - 1.04 µm2 (6T)	XC3S50A block RAM (8T), config cells (large 6T) http://www.chipworks.com/about-chipworks/overview/blog/review-tsmc-28-nm-process-technology (dense 6T)
65 nm	0.95	1.0 - 1.2	9 - 12	14500 - 31500 nm			AM1707, BFSC100F144
45 / 40 nm	0.95	0.9 - 1.2	6 - 11	7100 nm		1.38 µm2 (8T)	XC6SLX4
32 / 28 nm	0.92	0.85 - 1.05	11 - 12			0.16 µm2 (6T)	http://www.chipworks.com/about-chipworks/overview/blog/review-tsmc-28-nm-process-technology
22 / 20 nm	0.87	0.9 - 0.95	9 - 15
16 / 14 nm	0.72	0.85	13 + MiM		54 nm	0.058 µm2 (6T)	ChipWorks Intel 14nm