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mcmaster:pr0ndexer_protocol

loosely resembles what I actually implemented

Framing: SLIP with following payload bytes

  • 1 byte: checksum or CRC
  • 1 byte: sequence number
  • 1 byte: opcode/register
    • Want a bit for read/write
    • Use I2C convention? “7-bit address of the slave…followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave”
    • Prefer that its the high bit so register numbers are un-ambiguous
    • A read responds with the register value/response in the same packet format
  • 4 byte: value argument

bit 0 is least significant bit. All signed integers are 2's compliment

Opcodes:

Address Mnemonic Description
0x00 Misc block
0x00 MISC_STATUS
0x01 MISC_CONTROL
0x20 X block
0x40 Y block
0x60 Z block

MISC_STATUS:

MISC_CONTROL:

  • 0: execute emergency stop

Axis blocks

All addresses offset by block base address

XYZ indicates X/Y/Z as appropriate

Address Mnemonic Description
0x00 Z block
0x00 XYZ_STATUS
0x01 XYZ_CONTROL
0x02 XYZ_STEP_SET Set the step register to value (2's compliment)
0x03 XYZ_STEP_ADD Adjust the step register by argument
0x04 XYZ_STEP_ADD Adjust the step register by argument
0x05 XYZ_VELMIN Minimum velocity in steps/second
0x06 XYZ_VELMAX Maximum velocity in steps/second
0x07 XYZ_ACL Acceleration/decceleration in steps/second**2

Step register (i32): the number of steps remaining to step. Should probably initiate an automatic read when it hits 0

XYZ_STATUS

XYZ_CONTROL

XYZ_STEP_SET: set the step register to value

  • value: i32

XYZ_STEP_ADD: adjust the step register by value

  • value: i32
  • detect overflows?
mcmaster/pr0ndexer_protocol.txt · Last modified: 2014/07/19 17:13 by mcmaster