Pure silicon is a mediocre conductor but when its doped (either positive “p” or negative “n”) it becomes much more conductive. One simple application of this is to make a diode by placing n doped silicon next to p doped silicon. These charges cancel out and leave a poorly conducting charge neutral area in the middle. By applying positive voltage to the positive p side and negative voltage to the negative n side, the like charges repel and push the charge neutral area closer. As voltage is increased the neutral area shrinks and allows current to flow freely. Note that iss also possible to get current to flow in the other direction by applying a high voltage (avalanche effect) but this is not used in digital logic.

MOSFETs build on diodes by adding a control terminal to adjust charge between two similarly doped areas. For example, when positive voltage is applied to the gate of a N MOSFET it conducts. Similarly, when a negative voltage is applied to the gate of a P MOSFET it conducts. While real devices have many other critical details, this is generally sufficient detail to reverse engineer digital logic: while a logic designer has to make the system work reliably, a reverse engineer generally assumes the system works reliably.

This (Wiki) image shows schematic symbols for different types of MOSFETs. When analyzing basic CMOS circuits only N MOSFETs (NFETs) and P MOSFETs (PFETs) are relevant. However, NMOS and PMOS also use depletion mode transistors. For most practical purposes, they can be inferred as resistors and the device physics can be ignored.

A note of caution: chip designers know this is how people think when they try to copy chips. They occasionally exploit real device physics even in digital logic to confuse reverse engineers (“traps”). For the meantime assume that circuits work as described above but be mindful that there are exceptions.

But what are those funny triangles next to some of them? Lets go a little deeper. This is a typical cross section (derivative work) of an N MOSFET:

Specifically it represents this schematic symbol (source):

Now we can understand that that triangle is a diode notation. In an N MOSFET, the source is N doped sitting in a P well. Thus the body forms a PN junction with the source and drain, connected in the middle of the channel. That is, applying a positive voltage to the body will conduct out either the source or drain. If the body is left unconnected it can generate some stray currents. By connecting the body to ground it reverse biases the PN junctions (particularly the body-drain) and helps prevent leakage as well as potential latchup conditions.

To make the final point, the “no bulk” version above is a discrete MOSFET. Since it isn't made in a well process there's no reason to have a P substrate. For example, it might simply be an N wafer with P doping just in the channel region (TODO: get some discrete MOSFET pictures. Maybe bad example due to self aligned gate practices).

Typical poly gate transistor from a typical standard cell based IC. Some of the contact metal can be seen on the bottom but the gate itself is poly.

In general, there are three types of FET technology (in chronological order):

• Early aluminum metal gate
• Polysilicon gate
• Metal gate w/ high-k dielectric

Within each of these, especially polysilicon gates, there are many variations.

Dominant type seen today. Original ones were true metal gate on an oxide as the name implies, but modern ones tend to use polysilicon instead.

Above: classical metal gate type. From left to right: source, gate, drain. Note that gate and drain are more or less identical in CMOS. Colors are from thin film interference indicating different layer thicknesses.

Above: now metal removed. Black gate area is probably salt from dissolved gate metal. Color difference is because its from a different chip, not etch process (although etching can also change color)

Above top: top metal. Bottom: Al and some SiO2 removed

Typical metal gate CMOS transistor as used in non-trivial chips (ie CPU). The control signal

Above textbook style metal gate transistors

See quiz for analysis

Main page

Contacts from left to right: collector, emitter, base. The collector forms the bulk of the well. Assuming its an NPN (which it may or may not be), you can also see the p-isolation in blueish-green around the edges. The base forms the larger white area around the emitter. Traces of the metal contacts can be seen as darker regions on the collector's pink area.

Discrete bipolar transistor from TO-3 package.

Another bipolar description: http://zeptobars.ru/en/read/ULN2003-per-element-die-annotation

Diffusion transistor. Does not use photolithography. Above image shows the mesa shape versus other transistor which were more or less flat.

Name comes from the physical mesa shape. Indications that this is because of the component geometries, but also read something that indicated its because they used acid (probably HF) to etch it out and it gets the shape because it etches more on the top by the time it gets to the bottom. Modern dicing is either through scribing or sawing.

Uses photolithography to print transistors. Has SiO2 passivation. Significantly reduced cost and significant increase in quality.

Wafer is put into a high temperature oven and doped by gas diffusing into the silicon.

“It is the world's worst transistor, you couldn't sell it as a discrete component: low cutoff frequency, very limited current range and an inferior noise figure. But no self-respecting analog IC designer would want to be without it. The reason: In either a CMOS or bipolar process no additional diffusions are required.” [“Designing Analog Chips”, Hans Camenzind]

From wiki:

• Point-contact transistor
• Bipolar junction transistor (BJT)
• Heterojunction bipolar transistor, up to several hundred GHz, common in modern ultrafast and RF circuits
• Grown-junction transistor, first kind of BJT
• Alloy-junction transistor, improvement of grown-junction transistor
• Micro-alloy transistor (MAT), speedier than alloy-junction transistor * =
• Micro-alloy diffused transistor (MADT), speedier than MAT, a diffused-base transistor * =
• Post-alloy diffused transistor (PADT), speedier than MAT, a diffused-base transistor * =
• Schottky transistor * =
• Surface barrier transistor * =
• Drift-field transistor
• Avalanche transistor
• Darlington transistor
• Insulated gate bipolar transistor (IGBT)
• Photo transistor
• Field-effect transistor
• Carbon nanotube field-effect transistor (CNFET)
• JFET, where the gate is insulated by a reverse-biased PN junction
• MESFET
• High Electron Mobility Transistor (HEMT, HFET, MODFET)
• MOSFET
• Inverted-T field effect transistor (ITFET)
• FinFET
• FREDFET, fast-reverse epitaxial diode field-effect transistor
• Thin film transistor, in LCDs.
• OFET Organic Field-Effect Transistor, in which the semiconductor is an organic compound
• Ballistic transistor
• Floating-gate transistor, for non-volatile storage.
• FETs used to sense environment
• Ion-sensitive field effect transistor, to measure ion concentrations in solution. * =
• EOSFET, electrolyte-oxide-semiconductor field effect transistor (Neurochip) * =
• DNAFET, deoxyribonucleic acid field-effect transistor * =
• Spacistor
• Diffusion transistor
• Unijunction transistor
• Single-electron transistors (SET)
• Nanofluidic transistor
• Multigate devices
• Tetrode transistor
• Pentode transistor
• Multigate device
• Trigate transistors (Prototype by Intel)
• Dual gate FETs have a single channel with two gates in cascode; a configuration optimized for high frequency amplifiers, mixers, and oscillators.
• Junctionless Nanowire Transistor (JNT)

Try to get examples of each of these